The present invention relates generally to the field of data communication. More particularity, the present invention concerns a generic design methodology of a new family of Field Effect Transistor (FET) Integrated Circuits (IC) made of a nonstandard industrial process. Thus, its direct applications include a variety of subsystem and system functions such as Master Slave D-type Flip Flop (MS-DFF), Divider, Bang Bang Phase Detector (BBPD), Frequency Detection (FD), Phase and Frequency Detection (PFD), Voltage Controlled Oscillator (VCO) and Phase Locked Loop (PLL) in an optical switch IC for data communication.
Optical Fiber has been used in voice and data communication for some time now due to its high bandwidth and excellent signal quality resulting from its immunity to electromagnetic interference. The inherent optical data rate from a modulated single-mode laser beam travelling through an optical fiber is expected to well exceed 1000 Gbit/sec. However, short of a completely optical communication system, the practically realizable bandwidth of fiber optical communication systems has been limited by the need of signal conversion between optical and electrical domain and the associated electronics hardware. While the usage of standard industrial CMOS (Complementary Metal Oxide Semiconductor) ICs, having a moderate speed capability, has already migrated into the electronics hardware for optical communication systems due to their advantage of low manufacturing cost, low operating power consumption, low supply voltage requirement and fairly good circuit density, FETs made of a nonstandard industrial process should still be employed for a variety of niche or as yet unforeseen future applications. For example, an IC made of a nonstandard CMOS process, called CMOS Silicon On Insulator (CMOS SOI), with an insulating substrate such as Sapphire, although quite expensive, processes the unique advantage of extremely low parasitic capacitance thus the potential of an operating speed even higher than that of a Bipolar IC made of a standard industrial process.
Notwithstanding the potential of these nonstandard FET ICs, to approach their fundamental speed capability in real circuits for such ultra high speed applications, a balanced systems design methodology must be developed.
The present invention is directed to a new family of FET ICs made with nonstandard industrial processes and a corresponding generic design methodology.
The first objective of this invention is to achieve a generic design methodology for a family of FET ICs made with nonstandard industrial processes with a reduced amount of signal ripple after the respective logic signal levels are reached following a switching operation.